Register Control (hsid_x_registers)

This module serves as an interface between the Register Interface and the accelerator’s RTL logic. This interface layer consists of two main parts:

1. Mapping registers to software-accessible memory addresses.
2. Connecting them directly to the hardware.

The address-to-register mapping is automatically generated by the reggen tool, based on definitions provided in a JSON file. In this project, that file is located at data/hsid_x_ctrl.hjson. In this section summarizes the list of registers, their offsets, and the bits used.

The RTL code generated by reggen is stored in the directory hw/src/hsid_x_ctrl_reg. This code should not be modified manually. Instead, it must be regenerated whenever the JSON file is updated. Additionally, the tool automatically produces the corresponding C header files and documentation in Markdown format under the sw directory. The entire process is automated through a Bash script located at bin/hsid-ctrl-reg-gen.sh.

Access to these registers at the RTL level is handled through hsid_x_registers, which connects the Register Interface to the generated code and exposes the relevant signals to the rest of the accelerator modules.

To ensure compatibility with X-HEEP, the Register Interface is implemented as a packed structure defined in hsid_x_reg_pkg.sv, located in the directory hw/src/hsid_pkg/rtl. Although SystemVerilog provides the interface construct to improve module connectivity¹, this project follows the approach used in X-HEEP for consistency.

The table below lists the available signals, their direction (read or write), and the conditions under which they are triggered. Some signals—such as start and clear—can only be triggered by software and are automatically reset to zero one cycle later, preventing them from remaining active longer than necessary.

Signal	Type	Trigger
start	Read and clear	—
clear	Read and clear	—
idle	Write	—
ready	Write	—
done	Write	interruption
error	Write	interruption
cancelled	Write	interruption
library_size	Read	—
pixel_bands	Read	—
captured_pixel_addr	Read	—
library_pixel_addr	Read	—
mse_min_ref	Write	interruption
mse_min_value	Write	interruption
mse_max_ref	Write	interruption
mse_max_value	Write	interruption

Other status signals—such as done, error, and cancelled—are asserted only when an interruption occurs, i.e., at the end of an operation. This allows the software to determine whether execution completed successfully, ended with an error, or was cancelled.

---

1. https://github.com/pulp-platform/register_interface ↩