Architecture

The figure below shows the modules that compose the HSpecID-X accelerator and the path followed by the HSPs, from memory reading to the retrieval of the minimum MSE value. Control signals have been omitted to avoid overloading the diagram.

The accelerator is configured through the slave Register Interface, using the addresses assigned in the integration project. The reading of the captured HSPs and the spectral library from memory is performed through the master OBI bus.

The process follows four main steps:

1. The captured HSP is fully transferred to the FIFO.
2. Next, the spectral library transfer begins. As data arrives, it is injected into the MSE module to compute all intermediate accumulators of channel 1 and 2.
3. Each time the transmission of a spectral signature is completed, the MSE is computed by summing the intermediate accumulators and dividing the result by the number of bands using an integer divider module.
4. Finally, the computed MSE value is compared with the previous results to detect the maximum and minimum values, which are sent to the Register Control.

Modules design

The modules that comprise the accelerator connected to X-HEEP are listed below, which are presented from the bottom up, in accordance with the bottom-up design methodology.

The developed modules are located in the hw directory, each containing a subdirectory for the RTL code (rtl) and another for testbenches and verification (tb).

The table below summarizes the implemented modules, indicating their name, code identifier, and location within the accelerator hierarchy.

Name	Code	Location
FIFO	hsid_fifo	Main core
Squared Difference Accumulator	hsid_sq_df_acc	Main core
Divisor	hsid_divisor	Main core
Mean Squared Error	hsid_mse	Main core
Mean Squared Error Comparator	hsid_mse_comp	Main core
HSID Main	hsid_main	Main core
Register Control	hsid_x_registers	X-HEEP integration
OBI Memory Controller	hsid_x_obi_mem	X-HEEP integration
HSpecID-X	hsid_x_top	X-HEEP integration